点击此处看仿真图形：http://img291.photo.163.com/yswhu/32190484/962972640.jpg
module module1(fin,wr,cs,din,fout,rst);
input fin,wr,cs,rst;
input [7:0] din;
output fout;
reg[9:0] count;
reg[7:0] step,step_temp;
reg fout;
//assign fout = count[SIZE-1];
always @(negedge wr or posedge fout or negedge rst)
begin
if(!rst)
begin
step = 1;
end
else if(!wr)
begin
if(!cs)
step_temp = din;
end
else
begin
if(step<step_temp)
step = step+1b1;
else if(step>step_temp)
step = step-1b1;
else step = step_temp;
end
end
always @(posedge fin)
begin
count <= count+step;
fout <= count[9];
end
endmodule
你可以通过这个链接引用该篇文章:http://yswhu.bokee.com/tb.b?diaryId=10560988
